Electrical engineering / Free calculator

ADC settling time

Estimate the settling time of a single-pole RC input for a full-scale step to within half an LSB.

01 Your inputs

Calculated on your device. Inputs are not transmitted or stored.

02 Your result

Enter your values and select Calculate.

InputRCADC input
Total source resistance R charges the total input capacitance C. The model excludes additional poles and switching effects. Symbolic model; not to scale.

The method

t=RC(N+1)ln(2)

A worked example

For 1 kΩ, 100 pF, and 12 bits, τ = 100 ns. A half-LSB target takes 13 ln(2) ≈ 9.011 time constants, or approximately 901.1 ns.

Assumptions & limits

Single-pole exponential response to a full-scale step; 1–32 integer bits. Includes only the RC model. Op-amp slew, switch resistance variation, kickback, multiplexing, multiple poles, and actual ADC acquisition timing need separate verification against the device data sheet.

Calculation source: Engineering Workbench calculation engine; model cross-checked against TI SBAA535A.

Reference: TI RC filter settling-time analysis

Explore Engineering Workbench ↗

Keep exploring

All engineering tools ↗